This invention relates to a counter circuit. More particularly, it relates to a counter circuit in which a plurality of stages of counters are connected in cascade and have their signal logic levels inverted using main clock pulses and sub clock pulses.
FIG. 1 is a circuit diagram showing the arrangement of a prior-art counter circuit. Referring to the figure, numerals 1, 2, 3, 5 and 6 designate main clock signal lines which are respectively supplied with a main clock signal, numerals 8, 9 and 10 sub clock signal lines which are respectively supplied with a sub clock signal, and numerals 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 22, 23, 24, 25, 26 and 27 signal lines. The arrangement further includes buffers 30, 36 and 44, transfer gates (hereinbelow, simply written as "gates") 31, 33, 34, 37, 39, 42, 43, 45 and 47, inverters 32, 38 and 46, and AND gates 40 and 48.
In FIG. 1, a circuit formed of the parts 30, 13, 31, 14, 32, 15, 33 and 12 constructs a counter of the first stage, a circuit formed of the parts 36, 17, 37, 18, 38, 19, 39 and 20 constructs a counter of the second stage, and a circuit formed of the parts 44, 24, 45, 25, 46, 26, 47 and 27 constructs a counter of the third stage. Within an extent illustrated in FIG. 1, a binary counter of three stages is constructed. The parts 34, 40, 42 and 48 construct interstage coupling circuits.
Since the counters of the respective stages are structurally similar to one another, the mutually corresponding points thereof shall be respectively assigned common designations. In this specification, the parts 14, 18 and 25 shall be termed the `first points`, the parts 12, 20 and 27 and `second points`, and the parts 13, 17 and 24 the `third points`. The logic level of the third point is transferred to the first point by the main clock pulse, while the logic level of the first point is inverted by the inverter and the inverted level is transferred to the second point by the sub clock pulse. Signal transfer from the second point to the third point concerns a carry from the preceding stage, and will be described later.
Next, the operation of the circuit shown in FIG. 1 will be described. FIG. 2 is a time chart showing the operation of the circuit illustrated in FIG. 1. In FIG. 2, the axis of abscissas represents the time, and the voltage waveforms of the various signal lines depicted in FIG. 1 are vertically indicated by the same reference numerals. Since the voltage waveforms of the signal lines 15 and 19 are the inverted waveforms of those of the signal lines 14 and 18 respectively, they are omitted. The signal on the signal line 1 is the main clock pulses, while the signal on the signal line 8 is the sub clock pulses, and they have periods equal to each other. In the illustrated embodiment, the main clock pulse and the sub clock pulse have a phase difference equal to a half cycle. The phase difference, however, need not always be the half cycle, but can be set at any desired value within the limits in which the main clock pulse and the sub clock pulse do not overlap.
At a time t.sub.1, the respective signal lines are in the state of FIG. 2 in which all the first points, namely, the signal lines 14, 18 and 25 (the signal on the line 25 is not shown) of the counters of the respective stages are of logic "1" while the signal lines at other points are of logic "0". The logic "1" state of the signal lines 14, 18, and 25 is generated in the circuit of FIG. 1 upon operation of the counter circuit and is set as an initial state. For simplicity, only the states of signal lines 14 and 18 are illustrated, and, therefore, the states of signal lines of the third counter are omitted. When, at a time t.sub.2, the main clock pulse is impressed to enable the gates 31, 37, and 45 the logic levels on the first points or the signal lines 14, 18, and 25 become the same as the logic levels on the third points or the signal lines 13, 17, and 24 respectively. Since the states of the signal lines 13, 17, and 24 are of logic "0" at this time, the logic levels on the signal lines 14, 18, and 25 are changed and become "0". The logic levels on the signal lines 15, 19, and 26 become "1", but, since the gates 33, 39, and 47 have not been enabled, the logic levels on the signal lines 12, 20, and 27 remain in the previous state, namely, logic level "0". As a result, the logic level on the signal line 13 remains at "0", while the logic levels on the signal lines 17 and 24 are at "0" due to the disablement of the gates 34 and 42. However, at a time t.sub.4 when the main block is "0" and the sub clock becomes "1" to enable the gates 33, 39, and 47, the logic levels on the second points or the signal lines 12, 20, and 27 take the logic level "1" of the signal lines 15, 19, and 26, respectively, to become the inverted levels of the logic level on the first points or the signal lines 14, 18, and 25. As a result, the logic level on the signal line 13 is changed from "0" to "1", but the logic level on the signal lines 16 and 23 remain unchanged because the gates 34 and 42 are disabled by the logic "0" of the signal lines and 14 and 18, respectively. Since the main clock pulses on the signal lines 1, 3, and 6 remain at "0", the logic elevels on lines 14, 18, and 25 are not changed and remain at "0". At a time t.sub.6, the main block is "1" and the gates 31, 37, and 45 are once again enabled. However, only the logic level on the signal line 14 changes to "1" due to the high logic level on the signal line 13. The logic levels on the signal lines 18 and 25 remain unchanged at "0" due to the low logic levels on signal lines 17 and 24. At a time t.sub.8, the operation is repeated as at the time t.sub.4, namely, the sub clock becomes "1" to enable the gates 33, 39, and 47. The logic levels on the signal lines 12, 20, and 27 become the inverted level of the logic levels on the signal lines 14, 18, and 25 and the logic level on the signal line 13 becomes the same as the logic level on the signal line 12. However, since the gate 35 is disabled and the gate 39 is enabled, the logic level on the signal line 17 becomes the inverted level of the logic level on the signal line 18.
In this way, the values of the respective signal lines are successively changed with time. When the logic levels on the first points or the signal lines 14 and 18 in the respective counters are considered as count values, these values change as "00", "01", "10" and "11". Since the succeeding stage may be enabled only in the case of the value "11", a signal obtained by passing the carry signal (14) of the first stage and the output signal (18) of the second stage through the AND gate 40 can be utilized as the carry signal of the third stage. That is, in the case of the multistage counter circuit, the carry signal of the preceding stage and the output signal of the particular stage are passed through the AND gate, and the resulting signal is utilized as the carry signal of the succeeding stage. In other words, the counter circuit is controlled so that the gate 34 may fall into the ON state at the count phase immediately before the carry at which the carry pulse is delivered from the preceding stage, namely, at the count phase "01" or "11" and that the gate 42 may fall into the ON state at the count phase immediately before the carry at which the carry pulse is delivered from the preceding stage, namely, at the count phase "11".
In the prior-art counter circuit as stated above, the carry signal of the preceding stage and the output signal of the particular stage are passed through the AND gate and then utilized as the carry signal of the succeeding stage. This has led to the problem that, as shown in FIG. 3, delays in the carry signal 14 of the preceding stage and in the output signal 18 of a particular stage incurs an error in the carry signal 22 of the succeeding stage and therefore, the counter circuit is incorrectly operated.